技能/経験

【Qualifications & Requirements】
・BA/BS Degree in Layout Design or related field or equivalent experience
・10 years’ experience with layout design for analog and full-custom digital blocks
・Experience TSMC 180nm, 65nm, 22nm process technologies
・Proficient in using layout editing tools in the Cadence Virtuoso design environment
・Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or　Mentor Calibre
・Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
・Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
・Experience in chip‐level floor planning and analog block integration
・Experience chip level integration, verifications, and tape-out
・Ability to use productivity‐enhancing tools and design scripts to further automate tasks is also desirable
・Must be able to lift, push, and pull up to 5 lbs

【Desired Characteristics & Attributes】
・Attention to detail, organized, accurate and can produce efficient layout techniques
・Has a good track record of on time work delivery
・Has a self-motivated, team player with good communication skills
・Ability to work well with others in a fast-paced collaborative team environment