Digital Design Engineer
想定年収
800万円 ~ 2,500万円
勤務地
東京都
仕事内容
・Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
・Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
・Developing standalone test benches to verify the RTL behavior.
・Writing and verifying SystemVerilog Assertions (SVA) for a design.
・Writing timing constraints and clock definition for synthesis and place and route tools.
・Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
・Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
・Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
・Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
・Post-Si bring-up, validation, and debugging.
募集人数
1人
応募条件
技能/経験
【Qualifications & Requirements】
・Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
・Excellent verbal and written communication skills in English.
・Proficient in Verilog and SystemVerilog.
・Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
・Experience in designing mixed-signal digital logic.
・Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
・Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
・Skilled in scripting languages Perl/Tcl/Python.
【Desired Characteristics & Attributes】
・Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
・2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
・2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
・Experience in complex FSM design.
・Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
・Experience in low-power digital design flow.
・Basic understanding of the Control Theory.
学歴
大学
職務経験
要
業界経験
要
年齢
年齢制限不問
英語力
中級以上
その他語学力
語学力詳細
English trainings are provided
勤務条件
雇用形態
無期雇用
試用期間
有り(3ヶ月)
給与
年俸制
年収：800万円 ~ 2,500万円
月収：67万円～
月額基本給：52万円～
賞与・インセンティブ
In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
昇給
有り
定期的な昇給はなし
勤務地
東京都
就業時間
09:00～18:00
休憩時間：60分
残業：月10時間～30時間程度
固定（定額）残業代制
残業手当
定額の残業代＋通常の残業代
固定残業時間 40時間 / 月
固定残業代 151,515円 / 月
固定残業時間超過分は別途支給されます。
通勤手当
交通費：全額支給
休日・休暇
完全週休二日制, 土, 日, 祝日, GW, 年末年始
年間休日：121
年間有給休暇：有給休暇は入社後4ヶ月目から付与されます
( 初年度 10日 4か月目から付与(入社日によって按分） )
社会保険
雇用保険, 健康保険, 労災保険, 厚生年金
求人No.：NJB2381570
最終更新日：2026/5/19