技能/経験

【Qualifications & Requirements】
・MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
・Good verbal and written communication skills in English
・Proficient in SystemVerilog and SystemVerilog OOP
・Fluency in utilizing scripting languages such as Perl / Python
・Proficient (through work experience) in verification using UVM
・Strong experience writing SystemVerilog Assertions (SVA)
・Understanding of Analog schematic and experience with Cadence Virtuoso
・Basic understanding of digital design using Verilog
・Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
・Ability to work independently and drive solutions to challenging problems

【Desired Qualification】
・Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques
・Experience with UVM-AMS methodology
・Solid experience with Formal Property Verification (FPV)
・Programming experience writing OOP code in C++
・Excellent written and verbal communication skills in English
・Experience with performing analog mixed-signal verification
・Proven track record in working well with others in fast-paced and collaborative work environment
・Knowledge of analog design
・Knowledge of synthesizable digital design
・Experience working on verification of datapath designs including filters