In this role, you will be responsible for synthesis and place and route using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus.

This role is based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:
Synthesis and Place and Route using industry standard tools for high speed CPU core design
Plan out resources, schedule, project PPA
Develop strategies to deliver reproducible design convergence results
Help to create and refine synthesis and PNR flow for the project team
Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure
Develop and recommend better design methodologies to enable better timing convergence
Plan out resources, schedule, project PPA
Guide and mentor junior engineers
PV convergence (including static timing and power analysis)
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
Scripting in an interpreted language, minimum TCL in addition to at least one other