技術系（機械設計・製造技術） - 組み込み・制御系
技術系（機械設計・製造技術） - LSI・IC・メモリ設計
技術系（機械設計・製造技術） - パッケージ開発

In this role, you will help build emulation infrastructure for a System-in-package for high-performance AI/ML engines. This role requires a strong technical background and a problem-solver mindset.

This role is hybrid, based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:
Help build a state-of-the-art hardware emulation ecosystem including,
Build flow for emulation models with optimum frequency and emulation footprint
Write emulation test-benches for single and multi chiplet models and transactors, monitors and harness components
Write test plans focusing on unique functional coverage, performance, power extraction and low level software development
Execute test plans, summarize the results and share feedback with project stakeholders
Develop synthetic components for custom transactors, monitors, checkers, etc…
Work across boundaries with architects, software and design/verification teams to define and improve the emulation platform

■休日：完全週休二日制, 土, 日, 祝日, GW, 夏季休暇, 年末年始

Experience & Qualifications:
Bachelor, Master or PhD degree in electrical, computer engineering or computer science
At least 2 years experience in emulation/design
Experience with Synopsys Zebu
Understanding of logic design and mapping design to emulation hardware
Knowledge in Verilog/system Verilog
Knowledge of emulation tools, flows, scripting and automation
Good problem solving skills, organizational and communication skills
Good English language skills (written and spoken)


Nice to Have:
Experience with Cadence Palladium
Knowledge of C, C++ or SystemC
Knowledge of RISC-V, CPU microarchitecture, machine learning, die-to-die, memory controllers, PCIe, UCIe
Understanding of verification
Fluency in Japanese
Japanese work visa

■職種未経験者：不可